The Company Says iHBM Cuts Thermal Resistance By Over 30%
SK Hynix unveiled its ‘iHBM’ technology on May 26, which significantly reduces heat generation by integrating a unified cooling element within the HBM package. (Photo source: SK Hynix)
SK Hynix has made a bold bet on solving the heat problem, which has emerged as the biggest challenge of the artificial intelligence (AI) semiconductor era. The approach involves placing cooling structures directly inside the HBM (High Bandwidth Memory) package.
SK Hynix unveiled its next-generation ‘iHBM’ technology on May 26, which applies an integrated cooling element called ‘ICE (Integrated Cooling Elements)’ directly inside the HBM package. The company plans to apply the technology starting with HBM5, its next-generation product.
As GPU performance competition intensifies in the AI semiconductor market, HBM is also rapidly increasing its number of stacked layers and speed. The problem is heat. Given HBM’s inherent architecture of stacking multiple memory dies vertically, internal heat is bound to rise sharply. In particular, the D2D PHY (Die-to-Die Physical Layer) region, where the GPU and HBM exchange data at ultra-high speed, is cited as a representative heat-concentrated area.
In the industry, there is an assessment that the core of the next-generation HBM competition is shifting beyond simple stacking technology to ‘thermal control.’ The reason is that if heat cannot be properly managed, performance, yield, and system stability can all be affected.
SK Hynix’s iHBM is characterized by its structural solution to this problem. Conventional HBM used an indirect structure in which generated heat escaped to the outside through the core die. In contrast, iHBM places ICE directly within the D2D PHY region, where heat generation is most severe, creating a separate heat discharge path.
ICE is a silicon-based cooling element that does not conduct electricity but has high thermal conductivity. It is akin to placing a heat dissipation block inside the HBM package. The company explains that this makes it possible to reduce thermal resistance by more than 30% compared to conventional designs. This means that more stable operation is achievable even in high-temperature and high-load environments.
Mass producibility was also taken into account. SK Hynix stated that it secured large-scale production stability by applying its core packaging technology, the MR-MUF (Mass Reflow Molded Underfill)-based Wafer Level Packaging (WLP) process, without modification.
Compatibility with existing customers was also enhanced. The technology was designed to maintain the existing System-in-Package (SiP) structure, enabling GPU and SoC companies to adopt it immediately without major design changes. This means that major AI semiconductor customers, including Nvidia and other big tech companies, can also reduce the burden of adoption.
Kim Eun-jin
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