Global standards body moves to relax HBM height limits from HBM4E, potentially easing technical bottlenecks in stacking more DRAM layers for AI‑driven demand
SK hynix’s HBM4 product. (Photo courtesy of Sk Hynix)
As the global body that sets international standards for semiconductors moves to relax the height standard for high‑bandwidth memory (HBM), attention is turning to whether the development and mass production of next‑generation HBM by memory companies such as Samsung Electronics and SK hynix will gain momentum.
With HBM supply to big tech firms tightening amid surging demand for artificial intelligence (AI), there is analysis that the relaxation of the standard could become a turning point for expanding productivity.
As of on March 31, according to industry sources, the Joint Electron Device Engineering Council (JEDEC) is reportedly reviewing a plan to relax the HBM height by expanding it from the current level to around 900㎛ (micrometer·one‑millionth of a meter).
JEDEC is a global organization that establishes international standards for semiconductors and electronic components and ensures chip compatibility among semiconductor companies such as Samsung Electronics, SK hynix, and Micron.
Because big tech companies refer to JEDEC standards when developing AI chips, memory companies must produce HBM in alignment with those standards.
The new standard is expected to apply from the seventh generation, ‘HBM4E’, onward. Given that the height standard for the fifth‑generation HBM3E is 720㎛ and for the sixth‑generation HBM4 is 775㎛, the relaxation is noteworthy.
HBM stacks DRAM vertically, and JEDEC’s height standard is directly linked to the number of stackable layers.
The stricter the height standard, the thinner the DRAM must be made, pushing companies up against technical limits.
By contrast, if the standard is relaxed, it becomes relatively easier to implement high‑stack HBM, such as 16‑layer or 20‑layer devices. The current flagship HBM products from memory companies are 12‑layer. The higher the number of layers, the greater the data capacity that HBM can handle.
JEDEC’s relaxation of the standard is interpreted as reflecting the reality that memory companies are hitting technical limits amid the expansion of the AI market.
Orders for HBM from big tech firms are pouring in, but the mass‑production pace of memory companies has not kept up, deepening the supply‑demand imbalance.
Within the industry, there is analysis that this relaxation could alleviate some production bottlenecks for memory companies. Next‑generation products may enter mass production faster than existing ones.
The need to process DRAM to extreme thinness will decline, and the burden of error control in the stacking process is expected to lessen.
In the back‑end (packaging) stage, where HBM technological capability is decisive, there is also the advantage of continuing to use existing equipment, the ‘TC bonder’ (thermo‑compression bonder), even after HBM4E.
Until now, it had been anticipated that producing next‑generation HBM would require the next‑generation packaging technology called ‘hybrid bonding’, which has not yet been stabilized.
For the time being, continued use of existing equipment is analyzed to offer benefits such as securing HBM yield (good‑die rate) and reducing production costs.
Lee Gyu‑bok, former president of the Semiconductor Engineering Society, said, “Memory companies are struggling to secure yield at the packaging stage, and with JEDEC’s relaxation of the standard, yield improvement can be expected,” and added, “Accordingly, HBM production volume may also increase.”
However, there are also voices saying that it remains to be seen whether this will greatly help domestic companies.
An industry official said, “The leading companies, Samsung Electronics and SK hynix, are already producing at a level higher than the standard,” and added, “Relaxation of the standard may instead be advantageous to latecomers.”
Kim Eun-jin
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