Both Companies Aim to Leverage Advanced Processes to Gain a Competitive Edge in the Upcoming HBM4E Market
SK hynix’s HBM structure mockup which was unveiled GTC-2025. The base die (logic die) is placed on the interposer. (Photo courtesy of SK Hynix)
Amid the surging importance of high-performance High Bandwidth Memory (HBM) due to the explosion in Artificial Intelligence (AI) demand, competition over the logic die (base die), which acts as the brain of HBM, is also intensifying. In particular, starting with the 7th-generation HBM4E, Samsung Electronics and SK hynix are expected to engage in a performance battle by applying advanced processes to their base dies.
According to industry sources on March 23, the importance of the base die strategy is projected to grow even more in the HBM4E market, which is set to begin in earnest next year. The base die is the chip at the very bottom of the HBM stack that serves as a pedestal, connecting directly to the Graphics Processing Unit (GPU).
The base die acts as a channel connecting the GPU and the memory. In this situation, as AI demand has exploded, the data processing volume of GPUs has also surged, increasing the need to improve the performance of the base die. Accordingly, Samsung Electronics has enhanced its base die performance for the 6th-generation HBM4 by applying its advanced 4-nanometer process from Samsung Foundry. SK hynix has applied TSMC’s 12-nanometer process.
Following Samsung Electronics’ application of a 10-nanometer-class 6th-generation (1c) DRAM process, which is ahead of its competitors, and its adoption of an advanced foundry process for the base die, an assessment has emerged that it was able to secure an advantage over SK hynix in terms of HBM4 performance. The HBM4, which Samsung Electronics began shipping for mass production for the first time in the industry last month, achieves a data processing speed of 11.7 gigabits per second (Gbps) and supports speeds of up to 13 Gbps.
In response, SK hynix is reportedly reviewing a plan to apply TSMC’s 3-nanometer process to its base die starting from the 7th-generation HBM4E. This is interpreted as an attempt to compete with Samsung by boosting performance from HBM4E onwards. For its DRAM process, the company also plans to apply the 1c process instead of the existing 10-nanometer-class 5th-generation (1b). Samsung Electronics plans to apply the same 4-nanometer foundry process to its base die as in the 6th generation. However, it plans to achieve a higher performance of 16 Gbps while maintaining power efficiency by improving the performance of the transistors that control the flow of electric current.
In particular, an analysis suggests that starting from the 7th generation, the ‘Custom HBM’ market—where customers demand products tailored for power efficiency and performance improvements depending on the application—will open in earnest. This is increasing the need for base dies that apply finer line widths to add some logic functions, thereby enhancing computational performance and energy management efficiency. An industry official said, “The trend is that for next-generation HBM, base dies with advanced processes are being adopted to achieve the performance-per-watt or performance that customers want.”
Kim Eun-jin
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